1. Field of the Invention
This invention relates to a method for manufacturing VLSI MOS-transistor circuits wherein the source/drain regions of n-channel transistors or p-channel transistors are produced by ion implantation, using the gate as an implantation mask. The source/drain ion implantation is shielded by an additional spacer layer which is generated at the gate edges, and ohmic contacts are produced at the same time between the gate interconnect serving as a lead and the diffused regions in the semiconductor substrates which constitute buried contacts.
2. Description of the Prior Art
In the development of finer and finer structural dimensions of transistors in MOS logic and memory circuits, the dielectric strength, and the reduction of parasitic effects such as caused by an overlap capacitance between the gate and the source/drain regions are becoming increasingly significant. One method for resolving the problem is referred to as the LDD (lightly doped drain) transistor such as disclosed, for example, in an article by P. I. Tsang et al. in IEEE Trans. El. Dev. ED 29 (1982) pages 590-596. It is well known to produce LDD transistors with a technique referred to as the spacer technique. The preferred spacer material is SiO.sub.2 since it can be deposited conform by over steps, it electrically insulates, and can be etched to very precise dimensions. In the article by Tsang et al. the distance between the gate and the edges of the source/drain ion implantation is set over an oxide layer at the side wall of the transistor gate by an additionally deposited spacer oxide layer which is anisotropically etched before the source/drain ion implantation.
Another method utilizing a side wall spacer technique will be found in an article by I. Miyomoto et al. appearing in IEDM 83, pages 63-66. A spacer technique having a double layer of polysilicon and SiO.sub.2 is employed for manufacturing CMOS bipolar transistor circuits. This has the advantage that the end point for the etching of the polysilicon layer is recognizable so that an attack on the SiO.sub.2 is minium both on the field regions as well as the later diffused regions so that no damage of the single crystal substrate occurs. In contrast to SiO.sub.2, back-etching is more difficult in this location because a dimensionally true imaging of the polysilicon thickness along the steps is difficult to obtain a chlorine-containing plasmas, probably due to the granular structure of the layer. A thin auxiliary layer composed, for example, of SiO.sub.2 is used and the spacer structuring is undertaken by etching this double layer.